Wideband transmission-mode FET linearizer

ABSTRACT

A FET is operated without source-to-drain bias, with the source-to-drain conductive path coupled in series with a transmission line. A gate-to-ground impedance is selected in conjunction with a gate voltage near pinchoff to impress nonlinear distortion or gain and/or phase of signals traversing the source-to-drain conductive path. The nonlinear distortion can compensate for the amplitude distortion of a following amplifier, but the phase distortion may not be suitable for correcting that of the following amplifier. An inductor is bridged from source to drain, and corrects the phase without excessive effect on the amplitude. The magnitude of the inductor may be adjusted to minimize nonlinear amplitude change without affecting the phase change, whereupon the phase change may be made independent of amplitude change. A resistor in series with the bridging inductor can be selected to render amplitude change independent of phase change. Two such independent amplitude and phase correctors may be cascaded.

BACKGROUND OF THE INVENTION

This invention relates to distortion linearizers, and more particularlyto FET distortion phase and/or gain linearizers.

Satellite communications systems are finding increasing use forinter-continental and intra-continental data and entertainmentinformation transfers. The basics of such systems are by now commonknowledge, and include earth stations for transmitting information to,and for receiving repeated or translated information from, a satellite,which is often geosynchronous. The high capital costs of communicationssatellites requires that the greatest possible use be made of theirfacilities, to lower the per-unit cost of communications. The severeoperating environment in space, coupled with the inability to access theorbiting satellite to effect repairs, places stringent requirements onthe systems and components of a satellite and its communication systempayload. A plurality of communications channels are ordinarily provided,with enhanced channel-to-channel isolation by use of combined frequencyand polarization diversity, as described in U.S. patent application Ser.No. 07/772,207, filed Oct. 7, 1991 in the name of Wolkstein. Theinformation signal at the satellite must be amplified beforeretransmission back to earth for reception by an earth station. Inprinciple, the information signals received at the satellite could beamplified by a single power amplifier. However, because of the linearitylimitations of amplifiers which are available at the current state ofthe art for operation at the desired signal amplitude or power outputlevels, excessive intermodulation distortion occurs when multiplechannels are processed in a single amplifier.

In order to maximize of the life of the satellite, the weight of everyadditional component must be assessed against the reduction in theuseful lifetime of the satellite as a result of the reduced payload ofexpendable propellant (fuel or fuel-plus-oxidizer) which the componentdisplaces. Thus, the tradeoffs of communications system performanceversus weight are carefully evaluated. This evaluation is renderedcomplex because of other factors which must be considered, such as powerconsumption, reliability and payload performance.

As described by the aforementioned Wolkstein application, conventionalcommunications systems use individual power amplifiers in each channelto reduce intermodulation distortion. However, some forms of distortion,such as phase distortion dependent upon instantaneous signal amplitude,and signal compression with increasing signal level, are not amelioratedby the single-channel amplifying technique. In order to maximize theoutput power from the power amplifier in each channel, the signal levelis increased to a level at which significant distortion occurs, and adistortion corrector (often termed a pre- or post-equalizer) is added inthe amplifier signal path.

Many different types of equipments termed balancers, compensators andequalizers are used in systems generally and in communications systemsin particular. Thus, "balancers" may be weights used on rotating deviceswhich reduce physical vibration, or may include a potentiometerconnected to the electrodes of the tubes of a push-pull vacuum-tubeamplifier to reduce harmonic distortion by making the tube's operatingtransfer functions as similar as possible. A "compensator" may be gasdiverters affixed to the barrel of a small arm or cannon to reducerecoil, a magnet attached to compass, or it may be an electrical device,of which one example is a linear (nominally independent of amplitude)variable amplitude-versus-frequency (slope) device for maintainingconstant gain in transmission-line systems such as cable televisionsystems (CATV) in the face of different coaxial cable lengths or, whenthermally controlled, in the face of performance variations caused bydaily and seasonal temperature variations. Similarly, an "equalizer" maybe a mechanical apparatus for distributing a load across severalsupports or an electric conductor joining various equipotentiallocations in a circuit. Also, "equalizer" is another term for a variableor thermal cable compensator, as described above. A bridged tee slopeequalizer including complex reactive bridge networks is described inU.S. Pat. No. 4,967,169, issued Oct. 30, 1990 to Sun et al. A distortionequalizer corrects, in some way, for the distortion of an associatednon-linear circuit. A "predistortion" equalizer is a non-linearapparatus, inserted in the signal path between a signal source and anon-linear apparatus such as a signal amplifier, for predistorting thesignal in response to amplitude so that the amplitude andor phasedistortion introduced by the following non-linear stage is wholly orpartially cancelled. A post-distortion equalizer performs the samefunction at the output of the non-linear stage. Since the non-lineardevice for which compensation is required is usually a power amplifier,a post-distortion equalizer must handle higher signal amplitudes than apredistortion equalizer, for which reason predistortion equalizers arepreferred.

As mentioned, satellite system tradeoffs are carefully evaluated interms of power consumption, reliability, weight and performance. A greatdeal of attention has been directed to the tradeoffs between solid-stateamplifiers and travelling-wave tubes as channel amplifiers for satellitecommunications, and at this time both are being improved and both typesare currently used for frequency ranges from about 2 Gigahertz (GHz) to13 GHz. Distortion equalizers include transmission schemes such as thedual-gate, common-source FET scheme described in U.S. Pat. No.4,465,980, issued Aug. 14, 1984 to Huang et al, in which the signal isapplied to one gate, and detected signal from a signal sample is appliedto the other gate to generate the desired distortion. The signal sampleis produced by a directional coupler. Directional couplers appear inother predistortion circuits, such as U.S. Pat. No. 4,109,212, issuedAug. 22, 1971 in the name of Donnell et al; U.S. Pat. No. 4,283,684,issued Aug. 11, 1981 in the name of Satoh; U.S. Pat. No. 4,564,816,issued Jan. 14, 1986 in the name of Kumar et al; and U.S. Pat. No.4,588,958, issued May 13, 1986, in the name of Katz et al. These priordistortion equalizers have a salient disadvantage for satellite use, inthat they use directional couplers. Such directional couplers are oftendesigned as waveguide branch devices, which are assemblages of twoparallel "through" waveguides, with a plurality of "branch" waveguidesextending therebetween, which are dimensioned to produce the desiredlinear power division and linear phase shift. Such waveguide devicesmust have dimensions which are significant portions of a wavelength atthe frequency of operation, and so they cannot be miniaturized. As aresult, the waveguide directional coupler for a satellite predistortionequalizer, and possibly other components of some equalizers, tend tomake each distortion equalizer bulky and heavy. This is particularlydisadvantageous in multi-channel systems, because each channel includesa predistortion equalizer.

Reliability of satellite systems is enhanced by redundancy schemes. Inmany satellite communication systems, switched routing schemes allowhigh-priority signals to be routed to operative channels in the event ofa channel failure. Among the system portions which are more likely tofail are the amplifiers. Consequently, redundancy schemes often involveswitching the amplifiers among channels, together with supernumerary,ordinarily unused amplifiers, which can be switched into a channel toreplace a failed amplifier. A concomitant of such a redundancy scheme isthat each amplifier, and its associated distortion equalizer, must becapable of broadband frequency performance.

U.S. Pat. No. 5,038,113, issued Aug. 6, 1991 in the name of Katz et al,describes a transmission-type predistortion equalizer comprising an FETwith its source-to-drain conductive path coupled in series with atransmission line, in contrast to the above-mentioned Huang et alcommon-source arrangement, and with a gate-to-ground reactance and gatebias selected to produce the desired level of distortion of the signals.In general, this transmission-type FET acts as a lossy transmissionelement, in which the loss decreases with increasing signal, to producesignal expansion. The signal expansion with increasing signal leveloffsets the signal compression occasioned by the associated amplifier.The phase shift through the transmission FET is also affected by thesignal level. Several "modes" of operation of the Katz et altransmission FET distortion equalizer have been identified, which dependupon the gate bias voltage and the gate impedance. Three modes, eachwith about 5% bandwidth, have been identified, with both increasing anddecreasing phase shift as a function of increasing signal level. Afourth mode provides gain expansion at frequencies below about 3 GHzwith the FETs currently available. A fifth mode of operation isrelatively broadband, and provides useful gain expansion at and aboveKu-band (about 12 GHz). While this fifth mode of operation provides gainexpansion in a region which is of interest at certain satellitecommunication frequencies, it provides phase shift which decreases (lesstime delay) with increasing signal power level, which may not besuitable for equalizing those amplifiers which have a similar phasedistortion. To equalize distortion for those amplifiers subject tosignal or gain compression together with decreasing phase shift inresponse to increasing signal power level, the distortion equalizer musthave gain expansion coupled with phase shift which increases (more timedelay) with increasing power level.

A copending patent application entitled, "Balanced Reflective NonlinearProcessor using FET," Ser. No. 07/753,164, filed Aug. 30, 1991 in thename of Katz et al, describes a reflective, balanced arrangement oftransmission FET distortion generator operated in a reflective mode,which provides gain expansion together with increasing phase shift, as afunction of increasing signal power level. This arrangement uses acoupler as part of the reflective balanced arrangements.

An improved distortion generator is desired.

SUMMARY OF THE INVENTION

A distortion generator includes an FET including a gate electrode andalso including a controllable signal path extending between source anddrain electrodes. The controllable path is coupled in a signaltransmission path. The gate electrode is coupled to reference potentialby a selected reactance, and is biased to provide the desired distortionof the signal traversing the controllable path. For use as a linearizerin conjunction with signal processors exhibiting gain compressiontogether with decreasing phase shift in response to increases in signallevel, an inductance is coupled across the controlled signal path of thedistortion generator FET. The inductance provides a linear shunt path bywhich signal tends to bypass the FET path, principally when the FET pathis in a high-impedance state, so the signal flows principally throughthe inductance. When the FET path has a low impedance, the effect of theinductance is reduced. In a particular embodiment of the inventionadapted for use in the 11 to 13 GHz range, the inductance is provided bya discrete air-core solenoidal coil. In another embodiment of theinvention, adjustment of phase control substantially independent of gainexpansion control is provided by a resistance serially coupled with theinductance to form a series combination coupled between the source anddrain electrodes of the FET. At a particular value of the resistance,the phase change in response to signal power level is approximatelyzero, and the FET distortion generator provides only gain expansion withincreasing signal level. In yet another embodiment of the invention, twosource-to-drain FET paths are cascaded, one of which is bridged by aninductance, the other by an inductance in series with a resistance. Theresistance is selected to minimize phase change as a function of signallevel, whereby the value of the corresponding inductance controls theamount of expansion in response to signal level changes. The FET bridgedby an inductance then provides the phase change as a function of signallevel. An intermediate amplifier may be used to maintain overall gain.In yet another embodiment, the bridging resistance is itself provided bythe source-to-drain resistance of an FET. A variable capacitanceassociated with the bridging inductance controls the net bridgingcapacitance. The variable capacitance may be in the form of a varactordiode. In those systems in which the size or weight of hybrid couplersis not a problem, the bridged-inductance FET may be used in a reflectivemode.

DESCRIPTION OF THE DRAWING

FIG. 1 illustrates the basic prior art FET distortion generator;

FIG. 2 plots computer-generated amplitude and phase responses as afunction of frequency of the FET distortion generator of FIG. 1 in aparticular operating mode, illustrating, as a function of increasingsignal level, relative phase delay in one frequency range, and phaseadvance in another frequency range;

FIG. 3 is a simplified schematic diagram of a distortion generator inaccordance with the invention, in which the FET source-to-drain path isbridged by an impedance.

FIG. 4 is a simplified block diagram of the arrangement of FIG. 3 inwhich the bridging impedance is an inductor;

FIG. 5 plots computer-generated amplitude and phase responses of the FETdistortion generator of FIG. 4 as a function of signal amplitude over afrequency range of 8 to 14 GHz;

FIGS. 6a and 6b are plots of phase and amplitude responses,respectively, measured on a distortion generator as in FIG. 4, over arange of 2 to 18 GHz;

FIGS. 7a and 7b are plots corresponding to those of FIGS. 6a and 6b,respectively, measured over the frequency range 11 to 13 GHz;

FIG. 8a is a simplified block diagram of the predistortion equalizer ofFIG. 4 cascaded with a traveling wave tube amplifier, and FIGS. 8b and8c are plots of measured phase and amplitude response, respectively, ofa cascade similar to that of FIG. 8a traveling-wave tube amplifier witha predistortion equalizer;

FIG. 9 is a plot of Carrier-to-Intermodulation (C/I) ratio versusbackoff for the linearized TWTA of FIG. 8a;

FIG. 10a is a simplified schematic diagram of a distortion generator inaccordance with the invention in which a resistor is serially coupledwith an inductor to form a series combination, and the seriescombination is bridged across the controller current path of a FET andFIG. 10b is a simplified schematic diagram of the series combination ofan inductor with a FET, in which the FET is a controllable resistor;

FIG. 11 is a simplified schematic diagram of a cascade of two distortiongenerators, one principally arranged for phase control as a function ofsignal level, and the other arranged for compression or amplitudecontrol;

FIG. 12a illustrates, in simplified form, an alternative impedance whichcan be used in place of an impedance of FIG. 3, and FIG. 12b representsthe impedance of the current of FIG. 12a;

FIG. 13 is a simplified block diagram of a reflective distortiongenerating system using distortion generators in accordance with theinvention; and

FIG. 14 is a general block diagram of a satellite with a multichannelcommunication system using predistortion generators in accordance withthe invention.

DESCRIPTION OF THE INVENTION

FIG. 1 is a schematic diagram of a prior art distortion generator asdescribed in the above-mentioned Katz et al U.S. Pat. No. 5,038,113. InFIG. 1, a source 10 of alternating signal is coupled by a transmissionline, illustrated by a coaxial transmission line symbol 12, to adistortion generator designated generally as 14. The impedance presentedto the distortion generator is illustrated as a resistor 16, anddepends, as known, upon the internal impedance of source 10 and thelength, attenuation and characteristic impedance of transmission line12. Distortion generator 14 includes a FET 18 having a source electrode20 connected to transmission line 12, and a drain electrode 22 connectedto an output transmission line represented by a coaxial transmissionline symbol 24. A utilization device or load is represented by aresistor 42. A source-to-drain conductive path 26 extends between sourceelectrode 20 and drain electrode 26, and its conduction is modulated orcontrolled by the voltage applied between a gate electrode 28 andconductive path 26. An impedance illustrated as a dashed block 30 iscoupled between gate 28 and ground (or other reference potential, ifdesired). As illustrated within block 30, the reactance may be providedby a capacitor 32. However, as described in the aforementioned Katz etal patent, the net reactance between gate and ground is inductivebecause of path length consideration. A bias voltage source designatedgenerally as 40 is coupled by an isolation or decoupling impedance ordevice represented as a resistor 41 to gate electrode 28, for biasingthe FET to a region of desired nonlinearity. Those skilled in the artknow that a resistor having a value of about 500 ohms or more may besuitable for decoupling in the circuit of FIG. 1, and also for providingcurrent limiting, and that series radio frequency chokes (RFCs) may beused instead if current limiting is not needed, and that shuntcapacitors may be used on the side remote from the RF to aid indecoupling. Bias voltage source 40 applies voltage between gateelectrode 28 and controllable path 26 by a path which includes isolationresistor 41 and either (or both) source impedance 16 and load impedance42, and the ground connection.

FIG. 2 plots modeled or calculated amplitude and phase response of FETdistoration generator as a function of frequency, with signal inputamplitude or level as a parameter, for the structure of FIG. 1 using aNEC type N673 FET. In FIG. 2, plot 210 represents the amplitude responseor gain of the structure of FIG. 1 with 0.1 nanohenries (Nh) ofinductance from gate to ground, at an input signal level of 0 dBm, andplot 212 represents the calculated gain response at the lower inputsignal level of -25 dBm. Plots 210 and 212 show negative gain, alsoknown as loss. As illustrated, plots 210 and 212 converge at about 13Ghz. Below about 13 Ghz, the amplitude response is about 5 to 15 dBgreater at high signal levels than at low signal levels, therebyindicating a gain expansion by a like amount as a function of, or"with", increasing signal level. The response illustrated by plots 210and 212 would provide gain expansion useful for correcting anamplifier's gain compression at frequencies from 8 Ghz (and possiblybelow) up to about 13 Ghz.

The calculated phase response of the structure of FIG. 1 at low inputsignal levels is illustrated by plot 214 in FIG. 2, and at high signalinput levels by plot 216. As illustrated by plots 214 and 216 in thefrequency range of about 11 to 14 Ghz, a phase advance (change in thepositive-phase direction) occurs as the signal level increases from lowto high levels while a phase lag occurs from 8 to about 11 Ghz. Clearly,such a response cannot correct over the complete frequency range 8 to 14Ghz for an amplifier phase response which either advances (becomes morepositive) or retards (becomes more negative) with increasing signallevel. In particular, it cannot correct over the entire frequency rangefor an amplifier which experiences a retarding or decreasing phase shiftwith increasing signal level. Thus, even though the amplitude responseor expansion as illustrated by plots 210 and 212 might be satisfactoryover the frequency range of 8 to 13 Ghz, the phase response is notsuitable for distoration correction of at least some amplifiers.

FIG. 3 is a simplified schematic diagram of a distortion corrector,equalizer or compensator 300 in accordance with the invention. In FIG.3, elements corresponding to those of FIG. 1 are designated by likereference numerals. FIG. 3 differs from FIG. 1 only in that a linearimpedance illustrated as a block 310 is bridged from source electrode 20to drain electrode 22, across controlled path 26. Controlled path 26 ofFET 14 is effectively coupled as a voltage divider with load 42. In thepresence of bridging impedance 310, two paths exist for the flow ofsignal from source 10 to load 42, a first non-linear path throughcontrolled path 26, and a second linear path by way of impedance 310. Itshould particularly be noted that, as FET 26 is operated essentiallywithout source-to-drain bias, and its source and load impedances (16 and42) are ordinarily equal, it does not act as an amplifier. Therefore,impedance 310 is not a feedback impedance, but rather might be styled a"parallel" or "feedforward" impedance.

It has been discovered that, when impedance 310 of FIG. 3 is aninductance, the phase control can be used over a broader frequency band.This may be understood by considering that the phase angle of the signalpassing through the FET at high power levels, represented by plot 216 ofFIG. 2, is principally capacitive (i.e. the signal passing through theFET is phase advanced). At low signal power levels, the phase angle atfrequencies above 11 Ghz is less capacitive, and even becomes slightlyinductive (phase lag) at frequencies above about 12 Ghz. At frequenciesbelow 11 GHz, the signal exiting the FET at low input power is phaseadvanced relative to that at high input power levels. When the FET pathis bypassed by an inductive impedance 310 as in FIG. 4, at high signalpower (low FET loss), the component of the signal which is contributedby the inductance is small in amplitude relative to the componentpassing through the FET, and makes little difference to the net phaseangle, which remains advanced. At low signal power (high FET loss), thephase advanced signal contributed by the FET is reduced in amplitude,whereby the phase delayed component contributed by the inductancebecomes relatively larger, and the net signal is thereby phase retardedor delayed.

FIG. 4 is a simplified schematic diagram of a distortion generator 400in accordance with the invention. In FIG. 4, elements corresponding tothose of FIGS. 1 and 3 are designated by the same reference numerals. Asillustrated in FIG. 5, the input and output transmission lines are striptransmission lines of the type well known in the art and often referredto as "microstrip", which is used for microwave integrated circuits ormonolithic microwave integrated circuits (MMICs). Within gate-to-groundimpedance block 30 of FIG. 4, the impedance includes twoseries-connected inductors 430a and 430b with a juncture 432therebetween, and a capacitor 434 connected from the juncture to ground.Bridging impedance 310 is an inductor 410 connected between sourceelectrode 20 and drain electrode 22. The decoupling impedance,designated generally as 41, includes radio-frequency choke (RFC) 541, ashunt or decoupling capacitor 542 to ground, a resistor 544, and afeedthrough capacitor 546. The term radio-frequency refers generally toany frequency above about 50 kHz which is capable of being radiated, andin relation to the described embodiments refers to microwave andmillimeter-wave. A gate source voltage Vg is applied a bias voltageterminal 540 from a source (not illustrated).

In a particular embodiment of the invention, inductors 430a and 430b ofFIG. 4 are each half-loops (i.e. similar to a Greek letter Ω) of 0.0007inch diameter (0.7 mil) conductive wire, each with wire length of 10mils. The actual inductance of such inductors is difficult to determinebecause the area included within the entire circuit loop contributes tothe inductance, so the inductance depends not only upon the half-loop"inductor" but also on the layout of the associated circuit. Capacitor432 has a value of 0.1 pF, and is used principally as a tie point forinductors 530. In this same embodiment, shunt inductor 510 consists ofthree similar half-loops connected in parallel to thereby simulate asingle large-diameter conductor, to thereby decrease the totalinductance. Each of the three half-loop conductors comprising inductor510 have 0.7 mil diameter and a wire length of 12 mils. The FET is aNippon Electric GaAs type NE673.

Plot 516 of FIG. 5 represents the calculated net phase response of thearrangement of FIG. 4 at the same high input power level of 0 dBm asthat of plot 216 of FIG. 2. At low input signal power, on the otherhand, the contribution by inductive shunt or bridging impedance 310causes a significant change in the net phase. The effect of the shuntinductance at low signal levels is to move the phase plot represented by214 of FIG. 2 in the negative phase direction (i.e. a phase lag),resulting in a net phase shift represented as plot 514 of FIG. 5. Asillustrated in FIG. 4, this change in phase between the high and lowsignal levels, as represented by plots 514 and 516, is relativelyconstant across the entire 8 to 14 GHz frequency band. The amplitudeexpansion in the presence of the shunt inductance, represented in FIG. 5by low-power plot 510 and high-power plot 512, is substantiallyunchanged from that represented by plots 210 and 212 of FIG. 2. Thus,the inductive bridging impedance results in a broad frequency range overwhich more consistent phase performance is achieved, without significanteffect on the gain.

FIG. 6a plots measured phase of the distortion generator of FIG. 4 overthe frequency range of 2 to 18 Ghz, with signal input amplitude as aparameter. The gate bias is about -0.95 volts. Markers 1 and 2 define 11and 13 GHz, respectively. Marker 3 is the frequency at which gaincrossover occurs, as described below. In FIG. 6a, plot 614 represents alow signal power level of -25 dBm input power, and plot 616 representsthe high input power level of 0 dBm. As illustrated, the difference inphase angle between the high and low power levels remains relativelyconstant over broad frequency ranges. FIG. 6b plots measured amplituderesponse of the structure of FIG. 4 over the frequency range of 2 to 18GHz for the same low (plot 610) and high (plot 612) signal amplitudes.Gain expansion occurs over the frequency range from 2 GHz to marker 3,which is at about 15 GHz. The gain expansion in the range 2-15 GHz,together with increasing phase angle with increasing signal power level,is desirable for compensating the amplitude compression and decreasingphase angle with increasing signal power exhibited by some amplifiersincluding traveling-wave tube amplifiers.

FIGS. 7a and 7b are expanded portions of plots 6a and 6b, illustratingdetails of the response in the frequency range of 11 to 13 GHz. Sincethe plots of FIGS. 7a and 7b are the same as those of FIGS. 6a and 6b,respectively, the same reference numerals are used. Also, the high powerlevel is 0 dBm and the low power level is -25 dBm, as in FIGS. 6a and6b. Performance such as that illustrated is useful in helping tocompensate distortion over at least some frequency bands used insatellite communications. Of course, other types of FETs and otherinductors may provide suitable performance over other frequency ranges.Absolute phase has no meaning. It is moved "all over" using phase offsetcontrol to keep display on the screening.

FIG. 8a is a simplified block diagram of a TWT amplifier (TWTA) 898cascaded with a predistortion equalizer 400 similar to that of FIG. 4,both coupled between source 10 and load 42. FIG. 8b illustrates plots ofthe phase response versus signal output amplitude of the arrangement ofFIG. 8a with a TWTA alone, and the TWTA together with a distortiongenerator as in FIG. 8a. FIG. 8c illustrates the amplitude response ofthe TWTA alone and with the predistortion equalizer. Plot 818 of FIG. 8brepresents the phase response of the TWTA alone. As illustrated, thephase of the TWTA begins at 0° reference value at low signal amplitude,and progressively becomes more negative with increasing input signallevel, for a total phase change of about 50° over the illustratedamplitude range. Plots 81150, 81175, 81200, 81225 and 81250 representsthe distortion-compensated phase versus signal input amplitude at 11.50,11.75, 12.0, 12.25 and 12.5 GHz, respectively. As illustrated, the plotsrepresenting compensated phase are congruent and constant at a referencevalue - 25° at lower levels, and no frequency plot deviates more thatabout 10° from the reference value during excursions from minimum tomaximum power. This is a significant improvement in phase performanceover the TWTA alone.

FIG. 8c illustrates a plot 810 of output signal amplitude versus inputsignal amplitude (compression or gain plot) for the abovementioned TWTAalone, and a group of plots, designated together as 812, representscorresponding plots at differing frequencies with the TWTA corrected bypredistortion apparatus 400 of FIG. 4. In FIG. 8c, marker 1 identifiesthe saturation power point of the TWT, which is the input power pointwhich produces maximum output power, and above and below which theoutput power decreases. As illustrated in FIG. 8c by plot 810, the TWTAalone goes into gradual compression beginning about 15 dB below thesaturation point, and reaches about 1 dB compression about eight dBbelow saturation. Distortion-corrected plots 812 are still almost linearat this power level, representing a gain of about seven dB of linearoperating level by comparison with the TWTA alone.

FIG. 9 plots two-carrier carrier-to-intermodulation (C/I) ratio versussignal level or power backoff from the single-carrier saturation of theTWTA with frequency as a parameter. In FIG. 9, plot 910 represents theperformance of a TWTA at 12 GHz, while plots 9120, 9125, and 9130represent the C/I ratio at 12, 12.5 and 13.0 GHz, respectively, for theTWTA cascaded with a predistortion equalizer according to FIG. 4. HigherC/I ratios represent better performance. As illustrated in FIG. 9, powerbackoff of 4 dB reduces the C/I ratio of the TWTA alone 20 dB, while thepredistortion compensated TWTA has C/I ratio greater than 32 dB. This isan improvement in C/I ratio of 12 dB, over a 16 GHz range, attributableto the distortion compensator. Several dB of C/I ratio improvement isprovided by the predistortion compensator at all frequencies in the 12to 13 GHz range, at all amounts of backoff to 10 dB.

It has been discovered that independent control of amplitude and phasechanges can be achieved. When bridge impedance 310 of FIG. 2 includes aninductance in series with a resistance, the magnitude of the resistancecan control the magnitude and direction of the change in phase shift.FIG. 10 illustrates a distortion generator similar to that of FIG. 4, inwhich bridge impedance 310 includes an inductor 510 in series with aresistor 1012. As modeled and calculated (not illustrated), the phasechange as a function of power level reaches zero at a resistor 1012value of about 300 ohms. This value of resistance has negligible effecton the change of gain as a function of signal level.

It has also been discovered that, when bridge impedance 310 of FIG. 4 isan inductance, the change in gain or compression as a function of signallevel can be adjusted without significantly affecting the change inphase. When the value of bridge or shunting inductance 510 is verysmall, it acts essentially as a short-circuit which bypasses thenonlinear FET conducting path 26. As a consequence, for very smallvalues of inductance, the change of gain as a function of signal levelor the nonlinearity of the distortion generator as a whole becomessmall. When the bridging inductance is large, a relatively large amountof the signal flows through the nonlinear FET path rather than throughthe linear inductor, with the result that the nonlinearity of thedistortion generator as a whole tends to be large. By judiciousselection of the inductance value, various amounts of nonlinearity canbe established.

FIG. 11 is a simplified schematic and block diagram of a cascade ofdistortion generators, one principally for controlling the amount ofamplitude distortion, the other for controlling the amount of phasedistortion. In FIG. 11, signal generator 10 with internal impedance 16drives a phase controlling nonlinear or distortion generator 1194. thephase-distorted output of generator 1194 is applied through anintermediate amplifier 1196 to compensate for the loss of distortiongenerator 1194, and the restored-amplitude signal is applied to anamplitude distortion compensating generator 1198. The phase andamplitude distorted signal at the output of distortion generator 1198 isapplied to the utilization apparatus, illustrated as a load resistor 42.Ordinarily, the load will be a power amplifier.

Phase distorting generator 1194 is similar to the arrangement of FIG. 4,and reference numerals are the same as those of FIG. 4, but in the 1100series. The bridge inductor is adjusted to minimize the change in gainas a function of signal amplitude. As mentioned, this still allowschange of phase with changes of signal amplitude. The gate of FET 1118of FIG. 11 is biased from a first controllable voltage source (notillustrated) which produces a gate voltage V_(G1) selected to optimizethe phase change as a function of signal amplitude.

Amplitude distorting generator 1198 is similar to the generator of FIG.10. In generator 1198, a FET 1158 has a controlled current path 1166extending from a source electrode 1160 to a drain electrode 1162, andalso has a gate electrode 1168. An impedance 1170 extends from gate 1168to ground. Gate electrode 1168 is biased from a source (not illustrated)by way of a terminal 1180 and isolation impedance 1181. The seriescombination of an inductor 410 and a resistor 1012 is bridged acrosscontrolled path 1166. Resistor 1012 is adjusted to minimize changes inphase as a function of signal amplitude, while inductor 410, gateimpedance Z_(g) and voltage V_(G2) are adjusted to optimize theamplitude distortion.

FIG. 12a is a schematic diagram of a bridging impedance 310 including aninductor 510 as in FIG. 4, and further including a capacitance in theform of a variable capacitor 1210 coupled across the inductor, tothereby form a parallel resonant circuit for bypassing the FET (notillustrated). FIG. 12b plots impedance Z versus frequency of the circuitof FIG. 12a. In FIG. 12b, dashed plot 1212 represents the impedance ofinductor 510 alone. If a larger effective inductance is desired over anoperating frequency range f₁ to f₂, variable capacitor 1210 of FIG. 12ais adjusted to parallel-resonate inductor 510 somewhat above frequencyf₂, to present an impedance across its terminals which is illustrated asplot 1214 of FIG. 12b. At frequencies below resonance, including theoperating frequency band f₁ to f₂, the inductance of inductor 510 has alower impedance than does the capacitance of capacitor 1210, andtherefore the current through bridging impedance 310 flows principallythrough inductor 510, and the net impedance of the parallel resonantcircuit is therefore inductive. Thus, the effective inductance of abridging inductor can be increased by parallel-resonating it at afrequency above the frequency band of interest. Naturally, such aparallel-resonant circuit, being effectively a single inductance, may beplaced in series with a resistor for purposes described above. FIG. 12crepresents the substitution of a voltage-variable capacitor 1280 forcapacitor 1210.

FIG. 13 is a simplified block diagram of a distortion generator inaccordance with the invention, used in a reflective mode. In FIG. 13, a3 dB, 90° directional coupler 1310 includes an input port 1312, whichcouples to output ports 1314 and 1316. A first distortion generatoraccording to the invention, designated 1320, is coupled to port 1314,and a second such distortion generator, designated 1322, is coupled toport 1316. The second or output RF ports of each generator 1320, 1322are short-circuited to ground. Thus, one of the source and drainelectrodes of distortion generators according to the invention arecoupled to an output port 1314, 1316 of directional coupler 1310, andthe other electrode is coupled to ground. The desired distorted signaloutput is taken from port 1318 of directional coupler 1310.

FIG. 14 is a simplified general block diagram of a satellitemultichannel communication system. In FIG. 14, a satellite body 1406 hasthereupon a polarizing grid arrangement 1408, vertically polarizedreceiving antenna 1412V and horizontally polarized receiving antenna1412H. Receiving antennas 1412V and 1412H are coupled to vertical andhorizontal signal processing arrangements 1410V and 1410H, respectively,located within body 1406. Signal processing arrangements 1410V and 1410Hprocess the received signals to produce signals to be retransmitted,which are broadcast by transmitting antennas 1432V and 1432H,respectively. Signal processing arrangement 1410H is similar to verticalprocessing unit 1410V, so only processing 1410V is described.

The vertically-polarized signals arriving at antenna 1412V by way ofpolarizing grid 8 includes a plurality of signals centered at differentfrequencies as described in more detail in U.S. patent application Ser.No. 07/772,207 filed Oct. 7, 1991, in the name of Wolkstein. In atypical satellite system, there may be as many as 10 or more vertical(V) and 10 or more horizontal (H) channels, with their frequencies ofoperation interleaved. The bandwidth of a received signal may besufficient to carry a television channel, or more. Thus, the bandwidthof a signal may be 6 MHz or more. Vertical processing channel 1410V ofFIG. 14 may, as a consequence, receive 10 or more signals, each six ormore MHz wide, which are separated from each other by a like amount.Thus, the total frequency bandwidth occupied by the vertical signals maybe 120 MHz or more, calculated as [10(V)+10(H)]×6. The center frequencyof the 120 MHz band may be, for example, at 14 GHz.

The 10 or more vertical signals received by antenna 1412V of FIG. 14 arecoupled to an input filter 1414 of channel 1410V, for reducing noise andpreventing interference. Filter 1414 is a bandpass filter with abandwidth substantially equal to the total bandwidth of the verticalsignals. The filtered signals are coupled from input filter 1414 to alow noise amplifier (not illustrated) if required, and then to a blockconverter including a mixer 1416 and a local oscillator 1418. Thefrequency of local oscillator 1418 is selected to convert the 14 GHzcenter frequency to some other center frequency, such as 12 GHz. Thedownconverted 12 GHz signals are applied over a transmission path 1420to a multiplexing (MUX) filter 1422. Multiplexing filter 1422 separatesthe signals from each other in accordance with their frequencies.Multiplexing filter 1422 is the starting point for a plurality ofseparate channels designated generally as 1, 2, . . . 3, 4. If there are10 vertical signals, then the number of channels in signals processor10V is also 10. In effect, filter 1422 is a source of signals at aplurality of different frequencies, driving a like plurality of separatechannels.

In general, the signals on channels 1, 2, . . . 3, 4 in FIG. 14 areamplified, the distortion generated due to the amplification iscompensated, and the amplified and distortion corrected signals areapplied to a combiner or demultiplexer 1430, which may be a filtersimilar to filter 1422 operated in reverse, or it might be a group ofhybrid combiners which do not discriminate based upon frequency. Thecombined signals at the output of combiner 1430 are applied to atransmitting antenna 1432V for transmission back to an Earth station, orpossibly to another satellite.

System considerations such as the signal strength of the signalavailable at the satellite, the receiving antenna gain, and thetransmitting antenna gain and field strength required to reach theground station establish the overall power gain which must be providedin each channel between receiving antenna 12V and transmitting antenna32V.

Within any channel 1, 2, . . . 3, 4 of FIG. 14, the signal is processedby the cascade of a driver amplifier (DA) 1434, a distortion linearizersuch as a predistortion equalizer (PDL) 1436, and a power amplifier orfinal amplifier (FA) 1438. For example, as illustrated in FIG. 14, thecascade of a DA 1434¹, PDL 1436¹, and FA 1438¹ processes the channel 1signals, and a DA 1434², PDL 1436², and FA 1438² amplifies the signalsfor channel 2. As illustrated in FIG. 14, an additional cascade of a DA1434⁵, PDL 1436⁵, and FA 1438⁵ is connected in cascade, to define asupernumerary "channel" designated 5. Channel 5 is not connected forhandling signal, but instead represents a reserve cascade which may besubstituted into any of the other channels in which the cascade maybecome defective. To this end, connection between input filter 1422 andthe inputs of the various channel cascades 1434, 1436, 1438 is providedby means of an input switch arrangement designated 1424, and connectionbetween the outputs of final amplifiers 1438 and combiner 1430 isprovided by an output switch arrangement designated as 1428. A switchcontrol arrangement illustrated as 1426 gangs the input and outputswitches for simultaneous operation, and responds to signals in responseto evidence of failure, generated on the ground or autonomously bycontrol circuits with the spacecraft itself. Thus, in the event that thecascade of DA 14345¹, PDL 1436¹, and FA 1438¹ fails completely orbecomes degraded, the reserve cascade including DA 1434⁵, PDL 1436⁵, andFA 1438⁵ can be substituted therefor, with the cascade of DA 1434¹, PDL1436¹, and FA 1438¹ being removed from on-line use. Naturally,additional redundant units may be provided, and if the number offailures should exceed the number of redundant units, the switchingarrangement including 1424, 1426 and 1428 may move operable cascadesfrom lower-priority uses to higher-priority uses. In order to beswitchable to obtain this level of reliability, each cascade has aninstantaneous frequency bandwidth covering the cumulative or totalbandwidth of the vertical signals. Thus, a broadband linearizer such asthat of the invention is preferentially used for PDLs 1436.

Other embodiments of the invention will be apparent to those skilled inthe art. For example, any form of transmission line may be used tocouple signal to and from the distortion generator. A plurality of FETsmay have their controllable current paths paralleled for operation athigh power levels by joining their like electrodes for simultaneousoperation. While operation in a transmissive mode has been described,the structure of FIG. 3 or 10 may be operating in a reflective mode byshort-circuiting the output to ground. Also, the source and drainconnections of the FET may be reversed, if desired. For remote controlof the operating characteristics of the distortion generator, variablecapacitor 1210 of FIG. 12a may be implemented as a voltage-variablecapacitance diode.

What is claimed is:
 1. A circuit for, within a particular frequencyrange, distorting at least one of (a) amplitude and (b) phase of signalto be distorted, in response to the amplitude of said signal to bedistorted, said circuit comprising:a FET including a gate electrode, andalso including source and drain electrodes and a controllable path forthe flow of signal therebetween; bias means coupled to said gateelectrode and to at least one of said source and drain electrodes, forapplying bias voltage to said gate electrode for controlling said FETfor distortion of signals traversing said controllable path; reactancemeans coupled between said gate electrode and a point of referencepotential, said reactance means being selected to have a range ofvalues, within said frequency range, for coacting with said bias forcontrolling said FET for distortion of said signals traversing saidcontrollable path; inductance means including first and second ends;first coupling means coupled to said inductance means and to said FET,for coupling said first end of said inductance means to said source andsaid second end to said drain, for providing a path for flow of saidsignal parallel to said controllable path; and second coupling means forcoupling said signal to be distorted to one of said source and drainelectrodes, for causing said signal to traverse said controllable pathat least once, and for coupling the resulting distorted signal toutilization means.
 2. A circuit according to claim 1, wherein said firstcoupling means comprises low resistance galvanic connections, wherebysaid inductance means is coupled to said source and drain electrodes bylow impedances, and said source and drain electrodes are, at zerofrequency, constrained to be at the same direct potential.
 3. A circuitaccording to claim 1 wherein said second coupling means couples saidsignal to be distorted to said source electrode, and couples said drainelectrode to said utilization means.
 4. A circuit according to claim 1,wherein said inductance means includes a capacitor in parallel with aninductor, for generating a circuit parallel-resonant at a frequency,whereby the impedance of said parallel-resonant circuit is inductivebelow said frequency.
 5. A circuit according to claim 1, wherein saidfirst coupling means comprises resistance means.
 6. A circuit accordingto claim 5 wherein the value of said resistance means is selected tominimize changes of phase shift in response to the power level ofsignals traversing said circuit.
 7. A circuit for, within a particularfrequency range, distorting at least one of (a) amplitude and (b) phaseof signal to be distorted, in response to the amplitude of said signalto be distorted, said circuit comprising:a FET including a gateelectrode, and also including source and drain electrodes and acontrollable path for the flow of signal therebetween; bias meanscoupled to said gate electrode and to at least one of said source anddrain electrodes, for applying bias voltage to said gate electrode forcontrolling said FET for distortion of signals traversing saidcontrollable path; reactance means coupled between said gate electrodeand a point of reference potential, said reactance means being selectedto have a range of values, within said frequency range, for coactingwith said bias for controlling said FET for distortion of said signalstraversing said controllable path; impedance means including first andsecond ends, said impedance means having said first end coupled to saidsource electrode and said second end coupled to said drain electrode,for providing an alternate path for the flow of said signal between saidsource electrode and said drain electrode; and coupling means coupled tosaid signal to be distorted to one of said source electrode and saiddrain electrode, for causing said signal to traverse said controllablepath and said alternate path to thereby generate distorted signal, andfor coupling said distorted signal to utilization means.
 8. A circuitaccording to claim 7, wherein said impedance means comprises inductancemeans.
 9. A circuit according to claim 7, wherein said impedance meansis linear.
 10. A circuit according to claim 8, wherein said inductancemeans includes a capacitor in parallel with an inductor.
 11. A circuitaccording to claim 7, wherein said impedance means comprises inductancemeans serially coupled with resistance means.
 12. A circuit according toclaim 11, wherein said resistance means has a value selected to minimizechanges in phase shift in response to the power level of signalstraversing said circuit.
 13. A satellite, comprising:a body; antennameans mounted to said body for receiving signals to produce receivedsignals, and for transmitting signals to be transmitted; signalprocessing and multiplexing means coupled to said antenna means fordividing said received signals to produce separate signals in a firstplurality of independent channels; a second plurality of amplifiermeans; switch means coupled to said signal processing and multiplexingmeans for associating one of said amplifier means with each of saidchannels for producing amplified signals; signal combining means coupledto said switch means for demultiplexing said amplified signals toproduce a combined signal to be transmitted, and coupled to said antennameans for causing said combined signal to be transmitted; and aplurality of distortion linearizers, each associated with one of saidamplifier means, each of said distortion linearizers being, in at leastone position of said switch means, coupled for linearizing signals inone of said channels, each of said distortion linearizers including:(a)a FET including a gate electrode, and also including source and drainelectrodes and a controllable path for the flow of signal therebetween;(b) bias means coupled to said gate electrode and to at least one ofsaid source and drain electrodes, for applying bias voltage to said gateelectrode for controlling said FET for distortion of signals traversingsaid controllable path; (c) reactance means coupled between said gateelectrode and a point of reference potential, said reactance means beingselected to have a range of values, within said frequency range, forcoacting with said bias for controlling said FET for distortion of saidsignals traversing said controllable path; (d) inductance meansincluding first and second ends; (e) first coupling means coupled tosaid inductance means and to said FET, for coupling said first end ofsaid inductance means to said source and said second end to said drain,for providing a path for flow of said signal parallel to saidcontrollable path; and (f) second coupling means for coupling saidsignal to be distorted to one of said source and drain electrodes, forcausing said signal to traverse said controllable path at least once,and for coupling the resulting distorted signal to utilization means.14. A satellite according to claim 13, wherein said first plurality isless than said second plurality.
 15. A satellite according to claim 13,wherein each of said distortion linearizers is coupled in its ownchannel between (A) said signal processing and multiplexing means, and(B) said amplifier means associated with said own channel.
 16. Asatellite according to claim 13, wherein each of said distortionlinearizers is uniquely associated, in all positions of said switchmeans, with a corresponding one of said amplifier means.